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ADE7854/ADE7858/ADE7868/ADE7878
phase errors. For example, a current transformer (CT) with a
phase error of 0.1° to 3° is not uncommon. These phase errors
can vary from part to part, and they must be corrected to
perform accurate power calculations.
Data Sheet
acceptable; numbers outside this range are not accepted. If the
current leads the voltage, the result is negative and the absolute
value is written into the PHCAL registers. If the current lags
the voltage, the result is positive and 512 is added to the result
x
? phase _ resolution
, x ≤ 0 ?
+ 512 , x > 0 ?
?
The errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE78xx provides a means
of digitally calibrating these small phase errors. The ADE78xx
allows a small time delay or time advance to be introduced into
the signal processing chain to compensate for the small phase
errors.
before writing it into xPHCAL.
APHCAL , ?
BPHCAL , or ?
CPHCAL = ?
? x
?
? phase _ resolution
?
?
?
?
(8)
The phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) are 10-bit registers that can vary the time advance
in the voltage channel signal path from ?374.0 μs to +61.5 μs.
Negative values written to the PHCAL registers represent a time
advance whereas positive values represent a time delay. One LSB
is equivalent to 0.976 μs of time delay or time advance (clock
rate of 1.024 MHz). With a line frequency of 60 Hz, this gives
a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the
fundamental. This corresponds to a total correction range of
?8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is
?6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/
1.024 MHz).
Given a phase error of x degrees, measured using the phase
voltage as the reference, the corresponding LSBs are computed
dividing x by the phase resolution (0.0211°/LSB for 60 Hz and
0.0176°/LSB for 50 Hz). Results between ?383 and +63 only are
IAP
Figure 55 illustrates how the phase compensation is used to remove
x = ?1° phase lead in IA of the current channel from the external
current transducer (equivalent of 55.5 μs for 50 Hz systems). To
cancel the lead (1°) in the current channel of Phase A, a phase
lead must be introduced into the corresponding voltage channel.
Using Equation 8, APHCAL is 57 least significant bits, rounded
up from 56.8. The phase lead is achieved by introducing a time
delay of 55.73 μs into the Phase A current.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
As shown in Figure 54, APHCAL, BPHCAL, and CPHCAL
10-bit registers are accessed as 16-bit registers with the six MSBs
padded with 0s.
15 10 9 0
0000 00 xPHCAL
Figure 54. xPHCAL Registers Communicated As 16-Bit Registers
IA
IAN
VAP
VA
PGA1
PGA3
ADC
ADC
PHASE
CALIBRATION
APHCAL = 57
VN
1°
IA
IA
PHASE COMPENSATION
ACHIEVED DELAYING
VA
50Hz
VA
Figure 55. Phase Calibration on Voltage Channels
Rev. H | Page 40 of 100
IA BY 56μs
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